This invention relates generally to processing within a computing environment and, more particularly, to high performance cache directory error correction code (ECC) optimization.
In computing environments, the last few decades have been characterized by steady increases in processing speeds, which are represented by faster and faster cycle times. While this trend certainly offers benefits in terms of the usefulness of the computing environments for many applications, as cycle times have been pushed faster and faster, cache sizes have been forced to grow in size and capacity. The current caches may be, therefore, expensive and may frequently demand relatively large power supplies and relatively large portions of computing resources.
A result of the increase in cache size has been that generation of a directory hit in only one cycle has become increasingly unlikely despite the fact that not completing this type of action in one cycle requires that relatively large banks of latch registers must be provided to hold the look-up data from the directory or the partial hit determination. It is also advantageous to generate the hit as quickly as possible as this is a gating condition to a reading of the cache data out of the correct compartment in the cache. The amount of time it takes to read data out of the cache directly impacts when data is returned to the requestor (i.e., core) and, thus, the performance of the cache. The data is often appended with directory address tags, which are stored in, for example, static random access memory units (SRAMs) that are unfortunately vulnerable to soft fails and physical defects. Because of this, the address is stored with an ECC so that these errors can be detected and corrected.